Reference is made to FIG. 1 which is a schematic diagram of a standard six transistor (6T) static random access memory (SRAM) cell 10. The cell 10 includes two cross-coupled CMOS inverters 12 and 14, each inverter including a series connected p-channel and n-channel transistor pair. The inputs and outputs of the inverters 12 and 14 are coupled to form a latch circuit having a true node 16 and a complement node 18. The cell 10 further includes two transfer (pass gate) transistors 20 and 22 whose gate terminals are coupled with a word line node and are controlled by the signal present on a word line (WL). It will be recognized that the transfer (pass gate) transistors 20 and 22 may alternatively be separately controlled by signals on a first and second word line. Transistor 20 is source-drain connected between the true node 16 and a node associated with a true bit line (BLT). Transistor 22 is source-drain connected between the complement node 18 and a node associated with a complement bit line (BLC). The source terminals of the p-channel transistors in each inverter 12 and 14 are coupled to receive a high source voltage at a high voltage VH node, while the source terminals of the n-channel transistors in each inverter 12 and 14 are coupled to receive a low source voltage at a low voltage VL node. The high voltage VH and the low voltage VL comprise a power supply set of voltages for the cell 10. Conventionally, the high voltage VH is a positive voltage (for example, 1.5V) and the low voltage VL is a ground voltage (for example, 0V). In an integrated circuit including the SRAM cell 10, this power supply set of voltages may be received at pins of the integrated circuit, or may instead be generated on chip by a voltage converter circuit which receives some other set of voltages received from the pins of the chip. The power supply set of voltages VH and VL are conventionally applied to the SRAM cell 10 at all times that the cell/integrated circuit is operational. It will be recognized that separate low voltage VL values may be provided for the sources of the nMOS transistors in the inverters 12 and 14 while separate high voltage VH values may be provided for the sources of the pMOS transistors in the inverters 12 and 14.
Reference is now made to FIG. 2 which is a block diagram of a static random access memory (SRAM) array 30. The array 30 includes a plurality of SRAM cells 10 arranged in an matrix format. The number of cells 10 included in the array 30 can widely vary depending on the circuit designer's needs. The high voltage VH and the low voltage VL of the power supply set of voltages is applied to the array 30 and distributed over the array in a manner well known to those skilled in the art to the individual ones of the included cells 10 (for application to the source terminals of the p-channel and n-channel transistors as shown in FIG. 1).
The performance of the SRAM cell 10 is constrained by two independent operations. The first operation is a read operation and the constraint concerns the time between the triggering read signal to a valid output. The second operation is a write operation and the constraint concerns the time between the triggering write signal to next possible triggering signal to ensure proper write. Due to the write-margin constraint, the write port of the SRAM cell 10 has to be sized such that the slowest pass-gate nMOS transistor must be able to overcome the strength of fastest (feedback) pull up pMOS transistor. To manage a preferred low area design, and further so as to limit leakage, the pass-gate nMOS transistor cannot be sized very large, and this results in a pMOS transistor that cannot be made very strong. In this configuration, it is the pMOS transistor that ends up defining the write time of a cell and thus limits the overall SRAM cell performance at low voltages.
To address the issue of providing an SRAM cell better suited to a low voltage implementation, it is known in the art to decouple the read and write ports of an SRAM cell. With such a configuration, the circuit designer can instead size the read and write ports independently so as to ensure the correctness and efficiency of both operations.
Reference is made to FIG. 3A which is a schematic diagram of a multiple read access port static random access memory (SRAM) cell 110. This SRAM cell 110 presents an architecture wherein the read and write ports are decoupled. The heart of the SRAM cell 110 is a standard six transistor (6T) static random access memory (SRAM) cell 10 (like that shown in FIG. 1). The cell 10 includes two cross-coupled CMOS inverters 12 and 14, each inverter including a series connected p-channel and n-channel transistor pair. The inputs and outputs of the inverters 12 and 14 are coupled to form a latch circuit having a true node 16 and a complement node 18. The cell 10 further includes two transfer (pass gate) transistors 20 and 22 whose gate terminals are coupled to a word line node and are typically controlled by the signal present on a word line (WL). It will be recognized that the transfer (pass gate) transistors 20 and 22 may alternatively be separately controlled by signals on a first and second word line. Transistor 20 is source-drain connected between the true node 16 and a node associated with the a true bit line (BLT). Transistor 22 is source-drain connected between the complement node 18 and a node associated with a complement bit line (BLC). The true bit line BLT and complement BLC are provided primarily for write operations and the supporting circuitry is designed to support that write operation.
The multiple read access port static random access memory (SRAM) cell 110 further includes a plurality of read access ports 112, wherein each port 112 is coupled to a read line RL(1)-RL(n) (which is typically in the form of a bit line presented in addition to the true bit line (BLT) and complement bit line (BLC) for the cell 10). Each read access port 112 is controlled by the signal present on a read enable node associated with a respective read enable (RE(1)-(RN(n)) line. The corresponding read enable lines for the corresponding true and complement read access ports 112 are typically connected together (i.e., responsive to a single read enable signal), but it will be understood that the true and complement read access ports 112 may alternatively be separately controlled by signals on separate read enable lines. The read lines RL may be presented in true and complement forms, if desired. The read lines RL are provided primarily for read operations and the supporting circuitry is designed to support that read operation.
The source terminals of the p-channel transistors in each inverter 12 and 14 are coupled to receive a high source voltage at a high voltage VH node, while the source terminals of the n-channel transistors in each inverter 12 and 14 are coupled to receive a low source voltage at a low voltage VL node. The high voltage VH and the low voltage VL comprise a power supply set of voltages for the cell 10. It will be recognized that separate low voltage VL values may be provided for the sources of the nMOS transistors in the inverters 12 and 14 while separate high voltage VH values may be provided for the sources of the pMOS transistors in the inverters 12 and 14.
Reference is now made to FIG. 3B which is schematic diagram of an embodiment for a read access port 112 for use in the SRAM cell of FIG. 3A. The read access port 112 comprises a first transistor 116 whose gate receives the signal from the true node 16 or complement node 18 of the latch circuitry. The first transistor 116 is source-drain connected between a reference node (for example, the low voltage VL node) and an intermediate node 118. The read access port 112 further comprises a second transistor 120 whose gate is coupled to the read enable node and receives the signal present on the read enable (RE) line. The second transistor 120 is source-drain connected between the intermediate node 118 and a node associated with the read line RL.
Reference is now made to FIG. 3C which is schematic diagram of an embodiment for a read access port 112 for use in the SRAM cell of FIG. 3A. The read access port 112 comprises a first transistor 126 whose gate receives the signal from the true node 16 or complement node 18 of the latch circuitry. The first transistor 126 is source-drain connected between a first intermediate node 128 and a second intermediate node 130. The read access port 112 further comprises a second transistor 132 whose gate is coupled to the read enable node and receives the signal present on the read enable (RE) line. The second transistor 132 is source-drain connected between the second intermediate node 130 and the reference node (for example, the low voltage VL node). The read access port 112 further comprises a third transistor 134 source-drain connected between the first intermediate node 128 and a node associated with the read line RL. The read access port 112 further comprises a fourth transistor 136 source-drain connected between the first intermediate node 128 and another reference node (for example, the high voltage VH node). The gates of the third and fourth transistors 134 and 136 are coupled together and are further coupled to the read enable node and receives the signal present on the read enable (RE) line.
The configuration of FIG. 3A permits write access to the true node 16 and complement node 18 through the two transfer (pass gate) transistors 20 and 22 via the true bit line (BLT) and complement bit line (BLC) using the word line (WL), as well as read access to the true node 16 and complement node 18 through the two read access ports 112 via the true read line RLT and complement read line RLC using the read enable (RE) line.
If the standard six transistor static random access memory (SRAM) cell 10 (like that shown in FIG. 1) used within the SRAM cell 110 is specifically provided for supporting the write operation, the pertinent transistors can be sized to best enable and support write operations. However, the pMOS transistor sizing is still constrained by a total leakage budget, write-ability and write time constraints, and thus a decoupled solution, while an improvement over conventional 6T SRAM cell configurations, is still deficient, especially in low voltage applications.
The prior art also teaches the use of Schmitt trigger cell to enhance SRAM cell stability (see, Kulkarni, “A 160 mV Robust Schmitt Trigger Base Subthreshold SRAM,” IEEE Journal on Solid-State Circuits, vol. 42, no. 10, October 2007, the disclosure of which is incorporated by reference). The Schmitt trigger cell differs from the conventional 6T SRAM cell (FIG. 1) in the additional inclusion of four n-channel transistors connected in a manner well known in the art. However, the Schmitt trigger cell is not effective in terms of improving write operation (i.e., write-ability as well as write time).
Portable computers are reasonably pervasive today, and the trend is towards faster hand-held devices. These portable devices are expected to operate at much higher frequencies to enhance the user experience, and thus scaling of operating voltage is considered to be the most effective mechanism to reduce mobile device energy consumption. In this regard, high performance with a low voltage operation is desired. In the context of the modern system on chip (SoC) designs considered for such mobile devices, the included SRAM cells are recognized to substantially define the limits of possible voltage scaling (either because of performance or because of functionality). There is accordingly a need in the art for an SRAM cell design that addresses the deficiencies of the noted prior art in supporting low voltage operation.